Efficient verification/testing of system-on-chip through fault grading and analog behavioral modeling

textThis dissertation presents several cost-effective production test solutions using fault grading and mixed-signal design verification cases enabled by analog behavioral modeling. Although the latest System-on-Chip (SOC) is getting denser, faster, and more complex, the manufacturing technology is dominated by subtle defects that are introduced by small-scale technology. Thus, SOC requires more mature testing strategies. By performing various types of testing, better quality SoC can be manufactured, but test resources are too limited to accommodate all those tests. To create the most efficient production test flow, any redundant or ineffective tests need to be removed or minimized. Chapter 3 proposes new method of test data volume reduction by combining the nonlinear property of feedback shift register (FSR) and dictionary coding. Instead of using the nonlinear FSR for actual hardware implementation, the expanded test set by nonlinear expansion is used as the one-column test sets and provides big reduction ratio for the test data volume. The experimental results show the combined method reduced the total test data volume and increased the fault coverage. Due to the increased number of test patterns, total test time is increased. Chapter 4 addresses a whole process of functional fault grading. Fault grading has always been a ”desire-to-have” flow because it can bring up significant value for cost saving and yield analysis. However, it is very hard to perform the fault grading on the complex large scale SOC. A commercial tool called Z01X is used as a fault grading platform, and whole fault grading process is coordinated and each detailed execution is performed. Simulation- based functional fault grading identifies the quality of the given functional tests against the static faults and transition delay faults. With the structural tests and functional tests, functional fault grading can indicate the way to achieve the same test coverage by spending minimal test time. Compared to the consumed time and resource for fault grading, the contribution to the test time saving might not be acceptable as very promising, but the fault grading data can be reused for yield analysis and test flow optimization. For the final production testing, confident decisions on the functional test selection can be made based on the fault grading results. Chapter 5 addresses the challenges of Package-on-Package (POP) testing. Because POP devices have pins on both the top and the bottom of the package, the increased test pins require more test channels to detect packaging defects. Boundary scan chain testing is used to detect those continuity defects by relying on leakage current from the power supply. This proposed test scheme does not require direct test channels on the top pins. Based on the counting algorithm, minimal numbers of test cycles are generated, and the test achieved full test coverage for any combinations of pin-to-pin shortage defects on the top pins of the POP package. The experimental results show about 10 times increased leakage current from the shorted defect. Also, it can be expanded to multi-site testing with less test channels for high-volume production. Fault grading is applied within different structural test categories in Chapter 6. Stuck-at faults can be considered as TDFs having infinite delay. Hence, the TDF Automatic Test Pattern Generation (ATPG) tests can detect both TDFs and stuck-at faults. By removing the stuck-at faults being detected by the given TDF ATPG tests, the tests that target stuck-at faults can be reduced, and the reduced stuck-at fault set results in fewer stuck-at ATPG patterns. The structural test time is reduced while keeping the same test coverage. This TDF grading is performed with the same ATPG tool used to generate the stuck-at and TDF ATPG tests. To expedite the mixed-signal design verification of complex SoC, analog behavioral modeling methods and strategies are addressed in Chapter 7 and case studies for detailed verification with actual mixed-signal design are ad- dressed in Chapter 8. Analog modeling effort can enhance verification quality for a mixed-signal design with less turnaround time, and it enables compatible integration of the mixed-signal design cores into the SoC. The modeling process may reveal any potential design errors or incorrect testbench setup, and it results in minimizing unnecessary debugging time for quality devices. Two mixed-signal design cases were verified by me using the analog models. A fully hierarchical digital-to-analog converter (DAC) model is implemented and silicon mismatches caused by process variation are modeled and inserted into the DAC model, and the calibration algorithm for the DAC is successfully verified by model-based simulation at the full DAC-level. When the mismatch amount is increased and exceeded the calibration capability of the DAC, the simulation results show the increased calibration error with some outliers. This verification method can identify the saturation range of the DAC and predict the yield of the devices from process variation. A phase-locked loop (PLL) design cases were also verified by me using the analog model. Both open-loop PLL model and closed-loop PLL model cases are presented. Quick bring-up of open-loop PLL model provides low simulation overhead for widely-used PLLs in the SOC and enables early starting of design verification for the upper-level design using the PLL generated clocks. Accurate closed-loop PLL model is implemented for DCO-based PLL design, and the mixed-simulation with analog models and schematic designs enables flexible analog verification. Only focused analog design block is set to the schematic design and the rest of the analog design is replaced by the analog model. Then, this scaled-down SPICE simulation is performed about 10 times to 100 times faster than full-scale SPICE simulation. The analog model of the focused block is compared with the scaled-down SPICE simulation result and the quality of the model is iteratively enhanced. Hence, the analog model enables both compatible integration and flexible analog design verification. This dissertation contributes to reduce test time and to enhance test quality, and helps to set up efficient production testing flows. Depending on the size and performance of CUT, proper testing schemes can maximize the efficiency of production testing. The topics covered in this dissertation can be used in optimizing the test flow and selecting the final production tests to achieve maximum test capability. In addition, the strategies and benefits of analog behavioral modeling techniques that I implemented are presented, and actual verification cases shows the effectiveness of analog modeling for better quality SoC products.Electrical and Computer Engineerin

Charge density functional plus UU calculation of lacunar spinel GaM4_4Se8_8 (M = Nb, Mo, Ta, and W)

Charge density functional plus $U$ calculations are carried out to examine the validity of molecular $J_\text{eff}$=1/2 and 3/2 state in lacunar spinel GaM$_4$X$_8$ (M = Nb, Mo, Ta, and W). With LDA (spin-unpolarized local density approximation)$+U$, which has recently been suggested as the more desirable choice than LSDA (local spin density approximation)$+U$, we examine the band structure in comparison with the previous prediction based on the spin-polarized version of functional and with the prototypical $J_\text{eff}$=1/2 material Sr$_2$IrO$_4$. It is found that the previously suggested $J_\text{eff}$=1/2 and 3/2 band characters remain valid still in LDA$+U$ calculations while the use of charge-only density causes some minor differences. Our result provides the further support for the novel molecular $J_\text{eff}$ state in this series of materials, which can hopefully motivate the future exploration toward its verification and the further search for new functionalities

Competing states for the fractional quantum Hall effect in the 1/3-filled second Landau level

In this work, we investigate the nature of the fractional quantum Hall state in the 1/3-filled second Landau level (SLL) at filling factor $\nu=7/3$ (and 8/3 in the presence of the particle-hole symmetry) via exact diagonalization in both torus and spherical geometries. Specifically, we compute the overlap between the exact 7/3 ground state and various competing states including (i) the Laughlin state, (ii) the fermionic Haffnian state, (iii) the antisymmetrized product state of two composite fermion seas at 1/6 filling, and (iv) the particle-hole (PH) conjugate of the $Z_4$ parafermion state. All these trial states are constructed according to a guiding principle called the bilayer mapping approach, where a trial state is obtained as the antisymmetrized projection of a bilayer quantum Hall state with interlayer distance $d$ as a variational parameter. Under the proper understanding of the ground-state degeneracy in the torus geometry, the $Z_4$ parafermion state can be obtained as the antisymmetrized projection of the Halperin (330) state. Similarly, it is proved in this work that the fermionic Haffnian state can be obtained as the antisymmetrized projection of the Halperin (551) state. It is shown that, while extremely accurate at sufficiently large positive Haldane pseudopotential variation $\delta V_1^{(1)}$, the Laughlin state loses its overlap with the exact 7/3 ground state significantly at $\delta V_1^{(1)} \simeq 0$. At slightly negative $\delta V_1^{(1)}$, it is shown that the PH-conjugated $Z_4$ parafermion state has a substantial overlap with the exact 7/3 ground state, which is the highest among the above four trial states.Comment: 22 pages, 5 figure

Internet Customer Segmentation Using Web Log Data

The objective of this paper is to analyze web transaction log data that reveal customer behavior in the Internet channel, and to provide a useful online customer segmentation scheme. To achieve this, we analyze the relationship between the behavior of customers for online pet shops and revenue. We use the decision-tree method as a data-mining technique, and clustering analysis to segment customers.  We perform the study in two stages. First, we investigate the web transaction data of both the member customers and nonmember customers of a Korean online pet shop. Second, we narrow down the study focus and analyze only the member customers’ demographic data and their web transaction data. As a result, we obtain several meaningful segments based on customers’ transaction behavior and demographic characteristics. We use web log data to analyze customer transaction behavior and log-in information to analyze customer demographic characteristics. We discuss some strategic implications, for online shopping mall marketing, suggested by the acquired market segments

In situ-prepared composite materials of PEDOT: PSS buffer layer-metal nanoparticles and their application to organic solar cells

We report an enhancement in the efficiency of organic solar cells via the incorporation of gold (Au) or silver (Ag) nanoparticles (NPs) in the hole-transporting buffer layer of poly(3,4- ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), which was formed on an indium tin oxide (ITO) surface by the spin-coating of PEDOT:PSS-Au or Ag NPs composite solution. The composite solution was synthesized by a simple in situ preparation method which involved the reduction of chloroauric acid (HAuCl4) or silver nitrate (AgNO3) with sodium borohydride (NaBH4) solution in the presence of aqueous PEDOT:PSS media. The NPs were well dispersed in the PEDOT:PSS media and showed a characteristic absorption peak due to the surface plasmon resonance effect. Organic solar cells with the structure of ITO/PEDOT:PSS-Au, Ag NPs/poly(3-hexylthiophene):[6,6]-phenyl-C61-butyric acid methyl ester (P3HT:PC61BM)/LiF/Al exhibited an 8% improvement in their power conversion efficiency mainly due to the enlarged surface roughness of the PEDOT:PSS, which lead to an improvement in the charge collection and ultimately improvements in the short-circuit current density and fill factor. © 2012 Woo et al.1